Circuits and Techniques for 5G Mobile Communications and Low Power Sensors
|Peter Asbeck||Enrique Alvarez-Fontecilla|
|Ian Galton (Lead)||Hasan Al-Rubaye|
|Drew Hall||Varish Diddi|
|Patrick Mercier||Eythan Familier|
|Gabriel Rebeiz||Jefy Jayamon|
The project consists of five parts that are separate but are related in that they will develop critical circuits for 5G mobile communications and low power sensors.
Part 1 will explore several IC technologies for implementation of RF transmitter front-end chips for 5G systems with multiple antennas, and explore the linearity requirements and associated linearization techniques. To increase efficiency in backoff, architectures including Doherty and envelope tracking will be investigated. The impact on output fidelity of the mutual coupling between antennas will be examined. A major focus of the research will be on techniques that combine analog with digital predistortion techniques.
Part 2 will develop an interference cancelation technique applied to digital PLLs for frequency synthesis in 5G transceivers with carrier aggregation. In both 4G and anticipated 5G mobile communication systems, effective communication channel bandwidth is increased via carrier aggregation, i.e., combining multiple lower-bandwidth channels at different spectral locations. This requires multiple frequency synthesis PLLs to operate simultaneously at different frequencies on the same IC. A major practical problem is that each PLL output signal parasitically couples both modulated and unmodulated spurious tones into the other PLLs, often limiting overall performance. The research will develop an LMS-like algorithm to digitally measure the resulting interference components via correlation within the PLL and cancel them by introducing the opposite signals into the digitally controlled oscillator input, all in the digital domain.
Part 3 will develop computationally adaptive sampling and transmission techniques to extend the performance and efficiency of IoT/5G transceivers. The system to be developed consists of a low-noise amplifier with a switched bias scheme to have zero quiescent power, a low-power 10-bit SAR ADC using a novel charge recycling comparator (< 5 fJ/conv-step), a frequency tunable oscillator, an adaptive rate controller that determines the sampling frequency based on the signal activity, and an FSK transmitter. The novelty of this approach lies in quantifying the signal activity in a power efficient manner by computing the first and second order derivative of the signal. The objective is to reduce the power of the system to less than 50µW compared to 1mW using uniform sampling.
Part 4 will develop another technique for reducing power consumption in IoT receivers. It will reduce power consumption by avoiding PLL-based solutions in favor of a new architecture based on a single crystal, which can be readily found on any existing system, and a novel combination of injection-locked oscillators and variable frequency dividers. The target specifications are 16-QAM demodulation, 4Mbps data rate in 1MHz of bandwidth (compatible with Bluetooth channelization), -83 dBm sensitivity, all in <1mW of power consumption.
Part 5 will concentrate on the next generation of millimeter-wave phased arrays (60 GHz) and low-power radar sensors (80 GHz or 120 GHz) with emphasis on phased-array architectures for low DC power consumption while still maintaining excellent system-level capabilities. It will investigate different architectures for low-loss T/R switches including asymmetrical switches and bi-directional amplifiers, and do a full comparison between passive and active (vector modulator) phase shifters in terms of power consumption, linearity and bandwidth. It will also investigate power amplifier topologies with 10 dB output power control while still maintaining the same PAE, by using different size transistors connected in parallel. On the LO side, it will investigate the power consumption of a local oscillator and divider at 60 GHz for communications (80 GHz or 120 GHz for low-power radars) versus the use of an oscillator at 2x or 3x lower frequencies and a multiplier/amplifier chain. It will also study the transitions between the phased-array (or mm-wave radar) and the antennas, and how to decrease the transition loss and also increase the antenna efficiency. The goal is to tackle every aspect of the circuit and antenna systems so as to reduce the power consumption while still maintaining a strong communication the link or detection range in range, and to demonstrate an efficient communications link and/or low power radar sensor.
Publications by year
- E. Familier and I. Galton, “Second and Third-Order Successive Requantizers for Spurious Tone Reduction in Low-Noise Fractional-N PLLs,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2017, pp.1–4.
- Hasan Al Rubaye, Gabriel Rebeiz, "W-Band Direct-Modulation >20-Gb/s Transmit and Receive Building Blocks in 32-nm SOI CMOS" IEEE Journal of Solid-State Circuits, vol. PP, iss. 99, pp. 1-15, 2017
- V Vorapipat, CS Levy, P Asbeck, “Voltage Mode Doherty Power Amplifier," IEEE Journal of Solid-State Circuits, January 2017.
- V Vorapipat, C Levy, P Asbeck, "A Class-G voltage-mode Doherty power amplifier," 2017 IEEE International Solid-State Circuits Conference (ISSCC), 46-47, March 2017
- D.-G. Lee, P.P. Mercier, “Noise Analysis of Phase-Demodulating Receivers Employing Super-Regenerative Amplification,” IEEE Transactions on Microwave Theory and Techniques, 2017.
- Somok Mondal and Drew A. Hall, “An ECG Chopper Amplifier Achieving 0.92 NEF and 0.85 PEF with AC-Coupled Inverter-Stacking for Noise Efficiency Enhancement,” International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, May 29-31, 2017
- Somok Mondal, Chung-Lun Hsu, Roozbeh Jafari, and Drew Hall, “A Dynamically Reconfigurable ECG Analog Front-End with a 2.5× Data-Dependent Power Reduction,” Custom Integrated Circuits Conference (CICC), Austin, TX, May 1-3, 2017.
- E. Familier and I. Galton, “Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 6, pp. 836–847, Jun. 2016.
- Voravit Vorapipat, Cooper Levy, Peter Asbeck, "A wideband voltage mode Doherty power amplifier," Radio Frequency Integrated Circuits Symposium (RFIC), 2016 IEEE
- Narek Rostomyan; Jefy A. Jayamon; Peter Asbeck, "15 GHz 25 dBm Multigate-Cell Stacked CMOS Power Amplifier with 32 % PAE and ≥ 30 dB Gain for 5G Applications," 2016 11th European Microwave Integrated Circuits Conference (EuMIC), pp. 265-268, 2016
- Hasan Al-Rubaye, Gabriel Rebeiz, "A 20 Gbit/s RFDAC-Based Direct-Modulation W-Band Transmitter in 32nm SOI CMOS," 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)