Digital PLLs with Sub-100 fs jitter for Local Oscillator Frequency Synthesis
High-order modulation formats, such as 1024 QAM, enable very high wireless data rates with high spectral efficiency. However, the higher the modulation order, the higher the performance required of the phase-locked loops (PLLs) used for transceiver local oscillator generation. PLLs with sub-100 fs clock jitter are necessary for the high-performance modes of 5G, and it is likely that 6G jitter require- ments will be even more aggressive. Digital PLLs are particularly attractive for handset transceivers, but the few that have been published with sub-100 fs jitter have critical design challenges that make them temperamental to implement, and they have yet to be demonstrated in high-volume commercial products.
The research will address this problem by developing a digital PLL architecture capable of robust sub-100 fs jitter performance. The PLL will be a next-generation version of the FDC-PLL that was originally developed by our group and is currently in widespread commercial use. The enabling new feature will be a time amplifier prior to the phase detector that amplifies the time difference between cor- responding reference and divider edges. Unlike prior time amplifiers used in PLLs to reduce jitter, the new time amplifier has a wide useable input range and high linearity. The linearity will be further en- hanced via a digital calibration algorithm that measures error from time amplifier nonlinearity in real time (not as an autocalibration technique) and applies a correction signal to compensate for the error. A demon-
stration IC will be developed in 22 nm CMOS technology with a 76.8 MHz reference and an output fre- quency that spans 7-8 GHz, that targets an absolute jitter of less than 90 fs, in-band fractional spurious tones less than −65 dBc, and state-of-the-art power consumption from a 0.8 V supply.