The most significant sources of both static and dynamic nonlinear error in practical high-speed, high-resolution, continuous-time RF DACs are clock skew, component mismatches, and inter-symbol interference (ISI). Most published digital calibration techniques aimed at addressing these issues are only capable of reducing the static portion of such error, which leaves dynamic error as a major limitation. Techniques such as return-to-zero (RZ) signaling can be used to mitigate ISI, but they generally have undesirable side effects, such as halving the signal power and significantly increasing sensitivity to clock jitter, which greatly increase power consumption and/or decrease signal-to-noise-and-distortion ratio (SNDR). Consequently, clock skew, component mismatches, and ISI typically limit the Nyquist band SNDR of present-day CMOS RF DACs to less than 65 dB. Yet RF DACs with Nyquist band SNDRs of well over 65 dB are increasingly necessary in many high-performance applications including but not limited to 5G cellular base station transmitters. The proposed research will address this disconnect via on-chip digital calibration techniques that adaptively measure and cancel both static and dynamic DAC error from clock skew, component mismatches, and ISI in real time.

The difficulty that has prevented most published DAC calibration techniques from suppressing dynamic error arises from a property inherent to continuous-time DACs. Such DACs generate a continuous-time output pulse for each input codeword, and the output pulse has a bandwidth that far exceeds the DAC’s sample-rate because its duration is time-limited to one clock period. Therefore, any technique that cancels dynamic error either must do so over a bandwidth that is much wider than the DAC’s signal bandwidth, which is unlikely to be practical given the multi-GHz sample-rates required of RF DACs, or must perform frequency selective cancellation over a single Nyquist band. The proposed research will develop techniques that do the latter and demonstrate them via a DAC IC that targets best of class performance.

We have recently developed the first such technique that is fully automated (i.e., does not require manual tuning) [1]. The technique, called the mismatch-noise cancellation (MNC) technique, cancels static and dynamic error from clock skew and component mismatches over an RF DAC’s first Nyquist band. The initial version of the MNC technique, despite enabling a DAC IC that achieves a Nyquist-band SNDR of 77 dB [2], has two limitations: it oversamples the DAC output, which limited the sample-rate of the DAC IC in [2] to 600 MHz, and it does not cancel ISI. We have since proposed a subsampling version of the MNC technique that eliminates the oversampling requirement [3], but have yet to demonstrate it experimentally. The current phase of this research project involves the development of a new subsampling technique that cancels ISI over a DAC’s first Nyquist band and will demonstrate that the subsampling MNC and ISI cancellation techniques together enable best-of-class performance via a pair of 22 nm CMOS DAC ICs. A proof-of-principle 22 nm CMOS DAC IC enabled by the new techniques will be developed that targets record-setting performance: a worst-case Nyquist-band SNDR of 70 dB and a sample-rate of 6 GHz.