PROJECT OVERVIEW

The project consists of five parts that are separate but are related in that they will develop critical circuits for 5G mobile communications and low power sensors. Part 1 is improving output power, efficiency and linearity of power amplifier (PA) ICs for 28GHz operation. Part 2 is continuing the development of a new frequency-to-digital converter (FDC) based digital PLL architecture via new digital and time-based analog signal processing enhancement techniques. Part 3 is developing ultra-low power circuits and sensors for future IoT biosensors. Part 4 is implementing integrated circuits that sense and wirelessly communicate information from the body while being powered by a multi-input energy aggregating harvester. And Part 5 is continuing the development of phased-arrays for 5G communication links capable of handling Gbps.

FULL OVERVIEW
Chip on Needle

Professor Hall is developing ultra-low power circuits and sensors for future IoT biosensors. These BioMote sensors are the size of a single grain of rice and will be subcutaneously injected through a 16-gauge needle into interstitial fluid (ISF), the quasi-stationary extracellular fluid surrounding cells composed of nutrients, metabolites, and waste. ISF is highly correlated with blood enabling continuous, long-term biomarker monitoring. The batteryless device will be wirelessly powered through an inductive link that will also be used for bi-directional communication. Electrochemical biosensors will be incorporated on the BioMote to enable long-term, continuous biomarker measurements.

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Circuitry - Gabriel

Professor Rebeiz is continuing the development of phased-arrays for 5G communication links capable of handling Gbps. Its focus is on system-level investigation of techniques to reduce the cost of 64 and 256-element phased-arrays with single and MIMO beams. Specific areas of investigation include: 1) simple calibration (or non-calibration) methods to achieve excellent patterns over 0.4-1.2 GHz, 2) level of amplitude and phase calibration needed per element and per sub-array, 3) beam squint vs. frequency and scan angle and ways to mitigate it using sub-array calibration, 4) methods of on-chip self-calibration to take into account the various transmission-line lengths in the Wilkinson combiner, and differing antenna parameters (edge elements vs. center elements), 5) linearity of a phased-array in the presence of interferers, and 6) improvement in ACPR vs. backoff and a comparison between global (sub-array level) and local (channel per channel) optimization.

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Chip on a Finger

Our research involves implementing integrated circuits that sense and wirelessly communicate information from the body while being powered by a multi-input energy aggregating harvester. These circuits include sensor conditioning front-ends, analog-to-digital converters, wireless transceivers, and DC-DC converters.  Importantly, wireless communication should be standards-compliant to be commercially viable; proprietary radio systems without careful regard for operation in the presence of real-world interferers and without careful consideration of the power needed for higher PHY and MAC layers often do not work well in the real-world and severely underestimate power consumption.

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Mm wave amplifier

Circuits

High Efficiency Mm-Wave Power Amplifiers

Principal Investigator
Peter Asbeck

Our research  is about improving output power, efficiency and linearity of power amplifier (PA) ICs for 28GHz operation.  The primary technology employed has been CMOS-SOI at 45nm and 22nm nodes.  State-of-the-art performance has been obtained in most cases: individual PAs achieved PAE as high as 46% with 19dBm peak power; Doherty amplifiers were developed which achieve 28% PAE at 6dB backoff. 

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Circuitry - Ian

We are continuing the development of a new frequency-to-digital converter (FDC) based digital PLL architecture via new digital and time-based analog signal processing enhancement techniques. The objective is to systematically eliminate the limitations of present-day digital PLLs so as to elevate their performance well above that of the best present-day analog PLLs. Two next-generation IC prototypes are being developed that include techniques to increase loop bandwidth, reduce phase noise contributions from crystal reference noise and FDC flicker noise, and adaptively cancel error from DCO component mismatches.

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